NXP Semiconductors /MIMXRT1011 /PWM1 /MCTRL2

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Interpret as MCTRL2

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MONPLL_0)MONPLL

MONPLL=MONPLL_0

Description

Master Control 2 Register

Fields

MONPLL

Monitor PLL State

0 (MONPLL_0): Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.

1 (MONPLL_1): Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.

2 (MONPLL_2): Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset.

3 (MONPLL_3): Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset.

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